From a line of Verilog to a 336-billion-transistor AI accelerator: the 2 nm transistors now in volume production, the lithography that prints them, the packaging that stitches dies and memory together, and the research in Nature and on arXiv that points to what comes next.
A modern chip passes through roughly a dozen stages, each with its own tools and teams. Pick a stage to see what happens there, which tools do the work, and where AI is starting to help.
The FinFET carried the industry from 22 nm to 3 nm. At 2 nm the gate now wraps the channel on all four sides (gate-all-around nanosheets), power is moving to the back of the wafer, and the roadmap continues with stacked CFETs and 2D-material channels.
| Node | Company | Transistor | Power delivery | Status (Nov 2026) | Claimed gain |
|---|---|---|---|---|---|
| N3P | TSMC | FinFET | Front side | Volume; Apple A19 / M5 generation | Optimised 3 nm |
| N2 | TSMC | GAA nanosheet | Front side | HVM since Q4 2025; ~8% of wafer revenue in Q3 2026 | First TSMC GAA node |
| N2P | TSMC | GAA nanosheet | Front side | 2026 ramp | ~5% over N2 (reported) |
| A16 | TSMC | GAA nanosheet | Super Power Rail (backside) | Development complete; volume Q4 2026 or 2027 (sources differ) | 8–10% faster or 15–20% less power vs N2P |
| N2U | TSMC | GAA nanosheet | Front side | 2028 | 3–4% speed or 8–10% power, 1.02–1.03× density vs N2P |
| A14 | TSMC | 2nd-gen GAA | Front side (backside version = A12, 2029) | 2028 | Up to 15% speed or 30% less power vs N2 |
| A13 | TSMC | 2nd-gen GAA | — | 2029 | 6% area saving vs A14 |
| 18A | Intel | RibbonFET (GAA) | PowerVia (backside) | Shipping in Panther Lake since CES 2026; yields improving | First commercial backside power |
| 14A | Intel | RibbonFET 2 | PowerDirect (backside) | Customer decisions 2H 2026–1H 2027; volume ~2028 | Designed to use High-NA EUV |
| SF2 | Samsung | MBCFET (GAA) | Front side | 2025–26 ramp | Samsung's 3rd-gen GAA |
"N2", "18A" and the like are marketing names, not physical gate lengths. Compare nodes by measured density, speed and power on the same design. A 2026 teardown of Panther Lake put Intel 18A close to TSMC N3E in density, with newer TSMC nodes still ahead.
Wrapping the gate around stacked silicon sheets suppresses leakage at short channel lengths and lets designers choose sheet width per cell, trading drive current for power.
Moving power rails under the transistors frees front-side metal for signals, cuts IR drop and improves density. Intel shipped it first (PowerVia); TSMC follows with Super Power Rail in A16.
imec's 2026 roadmap sees complementary FETs (nMOS on top of pMOS) arriving around the A7 node (~2033), then 2D-material channels, and extends to A3 by 2038.
The smallest printable half-pitch follows the Rayleigh criterion, CD = k₁·λ / NA. EUV uses 13.5 nm light; High-NA EUV raises the numerical aperture from 0.33 to 0.55. Intel completed acceptance of ASML's EXE:5200B in late 2025 and is designing 14A around it, while TSMC has so far stayed with 0.33-NA EUV and multi-patterning.
k₁ below ~0.3 needs aggressive resolution-enhancement tricks; the physical limit for a single exposure is 0.25.
Every leading node since 7 nm uses EUV for its tightest layers. Below ~28 nm pitch, single exposures run out of room and fabs use two or more exposures per layer.
Anamorphic optics shrink the exposure field to half the standard reticle, so dies larger than ~26 × 16.5 mm must be stitched. imec targets qualification of its EXE:5200 by Q4 2026.
A High-NA scanner costs several hundred million dollars. Whether one exposure beats two cheaper ones decides when each foundry adopts it; analysts expect TSMC around the end of the decade.
A single reticle caps a die at ~830 mm². Today's AI accelerators exceed that by placing several compute dies and up to twelve HBM stacks on a silicon interposer (TSMC CoWoS), or by bonding dies directly on top of each other (SoIC). Memory bandwidth, not raw compute, often sets performance.
Presets: B300 · Rubin · MI455X · Samsung HBM4 max
Hybrid bonding joins dies copper-to-copper with micron-scale pitch. TSMC's A14-on-A14 SoIC (2029) promises 1.8× the die-to-die I/O density of N2-on-N2.
TSMC's COUPE photonic engine moves the optical transceiver next to the switch or GPU. TSMC claims 2× power efficiency and 10× lower latency than pluggable optics, with on-substrate production starting in 2026.
Public specifications as of November 2026. Vendor figures use different precisions and sparsity conventions, so compare like with like. Items marked reported come from secondary sources, not the vendor.
72 GPUs and 36 Vera CPUs (88 Olympus cores each) form a Vera Rubin NVL72 rack: 3.6 EF NVFP4. In full production, shipping 2H 2026.
The current volume workhorse in GB300 NVL72 racks. 1.5× the FP4 throughput of B200.
Announced roadmap item; figures are targets. Followed by the Feynman generation.
The first AMD GPU on TSMC 2 nm. 72 per Helios rack, with 50% more memory than a Rubin rack.
Google's seventh-generation TPU. Google says AlphaChip-generated floorplans have been used in recent TPU generations.
The first commercial chip with backside power delivery. Built at Fab 52 in Arizona; 18A yields still improving through 2026.
Apple's A19 and M5 generation is on TSMC N3P; reports say the next generation (A20, M6) moves to base N2. Rubin bandwidth is 22 TB/s in NVIDIA's developer blog and 19.2 TB/s in one NVIDIA spec table; MI455X bandwidth varies between reports.
A random defect kills the die it lands on, so the fraction of good dies falls exponentially with area. Splitting one large die into chiplets raises yield, at the cost of packaging and die-to-die interfaces. Adjust the sliders to see the trade-off on a 300 mm wafer.
Dies per wafer = π(d/2)²/A − πd/√(2A) for wafer diameter d. Murphy's model Y = ((1 − e^(−AD₀)) / AD₀)²; Poisson Y = e^(−AD₀). Chiplet cost here covers silicon only, not packaging, testing or the extra area for die-to-die links. Wafer prices for leading nodes are not published; ~$30k for N2 is a widely reported estimate.
A selection of peer-reviewed results and preprints from 2024–2026 that point to how chips will be built and designed next. Preprints on arXiv have not been peer reviewed.
A Fudan University team built a processor that runs standard 32-bit RISC-V instructions on 5,900 MoS₂ transistors, with a full standard-cell library for the 2D process. Atom-thin channels keep gate control at lengths where silicon leaks.
Nature 640, 654–661 →Two groups integrated complementary 2D logic, pairing n-type MoS₂ and p-type WSe₂ transistors on single chips. A 2026 Nature Communications paper adds wafer-scale, CMOS-compatible MoS₂ transistors with sub-5 nm channels.
Nature News & Views →"Universal photonic artificial intelligence acceleration" reports a silicon-photonics processor (a 128 × 128 photonic core) that runs ResNet, BERT and an Atari reinforcement-learning agent with near-electronic accuracy.
doi:10.1038/s41586-025-08854-x →Google's reinforcement-learning macro placer, published in 2021 and renamed AlphaChip in a 2024 addendum, has been used on TPU layouts. Critics questioned reproducibility and the use of commercial-tool initial placements; Google's rebuttal is "That Chip Has Sailed".
arXiv:2411.10053 →Benchmarks have moved from single Verilog modules to repository-level tasks. CVDP collects verification and design problems; HORIZON reports completing ChipBench, RTLLM, VerilogEval and nine CVDP categories hands-free, while stressing these are proxies, not solved hardware design.
arXiv:2606.28279 → CVDP →PDAGENT-BENCH defines 353 tasks across five capability axes for LLM and vision-language agents driving EDA tools in closed loop through placement, routing and timing closure.
arXiv:2606.17253 →imec places complementary FETs at the A7 node around 2033 and extends its logic roadmap to A3 in 2038, arguing that density gains now come as much from standard-cell height and wiring as from shrinking transistors.
Coverage →Samsung's 12-high, 36 GB HBM4 reaches 3.3 TB/s over 2,048 I/O, and NVIDIA and Broadcom presented co-packaged optical switches, signalling that I/O, not logic, is now the critical design frontier for AI systems.
ISSCC 2026 summary →Vendor and foundry figures are claims made by those companies. Roadmap dates move; check the primary source before relying on a date or specification.